Electronic storage devices are a key component for data retention in digital computing devices. Conventional semiconductor electronic storage devices, such as dynamic random access memory (DRAM) devices, include large numbers of capacitor and transistor structures that are grouped into memory cells in pairs. The capacitors in such devices, which are typically arranged in densely packed arrays to provide reduced device size and easy electrical interconnection, are used to temporarily store data based on their charged state. The memory cells that comprise a DRAM device are arranged into larger memory arrays.
The memory cells of a DRAM memory array are individually addressable via a word line and a digit line—one of which addresses a “column” of memory cells in the array, while the other addresses a “row” of memory cells in the array. In many DRAM devices, the digit line is buried below the capacitors, often below the upper level of the substrate on which the memory device is formed. For example, in once configuration, the digit line is buried within the isolation trench used for electrical separation of adjacent transistors.
To increase efficiency and reduce size of memory devices, significant resources have been devoted to the creation of smaller memory cells (that is, memory cells that occupy less “real estate”). The size of individual DRAM cells can be reduced in several ways. One way is to reduce the minimum size of the components, or “features”, that form the memory device. Decreasing the dimension of the minimum feature size F for a given manufacturing process generally occurs through the use of new and advanced lithography and etching techniques, such as through the use of “pitch doubling” techniques. Another way to reduce the size of individual DRAM cells is to design a smaller memory cell. Currently, commercially available DRAM chips have a memory cells size of 8 F2 or greater. U.S. Pat. No. 6,734,482 (issued 11 May 2004) describes a DRAM memory cell with a buried digit line that has a size 6 F2.
Vertical transistor designs are also used to decrease the size of memory devices. An example of a memory device using a vertical transistor is disclosed in U.S. Pat. No. 6,756,625 (issued 29 Jun. 2004), the entire disclosure of which is hereby incorporated by reference herein. In this design, the digit line is directly connected to a pillar used to form the vertical transistor.